1. Field of the Invention
The present invention generally relates to the fabrication and design of semiconductor chips and integrated circuits, and more particularly to a method of imparting radiation tolerance to a programmable logic device such as an application-specific integrated circuit (ASIC) having a design library which includes books of n-type and p-type semiconductor devices.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of a circuit into a layout is called the physical design.
Due to the large number of components and the details required by the fabrication process, physical design of an integrated circuit is not practical without the aid of computers. As a result, most phases of physical design extensively use computer aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. However, full custom design and production of a circuit can still be very time-consuming and costly, so circuit designers have turned to a more flexible approach using programmable logic devices such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) that contain standardized logic cells. One example of an ASIC is shown in FIG. 1. ASIC 2 has a plurality of input pins and a plurality of output pins, and further includes a variety of interconnected functional blocks placed on a substrate that are derived from the design library, including input/output (I/O) blocks, a core or microprocessor, an arithmetic logic unit (ALU), a digital signal processor (DSP), random-access memory (RAM), firmware or read-only storage (ROS), proprietary circuit macros (IP), and programmable logic. The programmable logic may be provided in the form of books 4 which contain rows of various semiconductor devices such as transistors and diodes, or other circuit elements such as capacitors and resistors, and can be used to create combinational gates such as AND, OR, NAND, NOR, and XOR gates as well as inverters, latches and more complicated logic structures.
FIG. 2 illustrates a typical construction for transistor books. The transistor book 4a of FIG. 2 has a first (upper) row of p-type field effect transistors (PFETs) located within a region of complementary (n-type) doping 6 (an implant well) referred to as an Nwell, and a second (lower) row of n-type field effect transistors (NFETs) located within a region of complementary (p-type) doping 8 referred to as an Pwell. Nwell 6 and Pwell 8 may extend vertically beyond the boundary of book 4a into adjacent books. The logic is programmed by applying a metallization layer that makes appropriate interconnections with the nodes of desired devices in the books.
One problem with this book construction is that, since each PFET shares the common Nwell 6 and each NFET shares the common Pwell 8, a radiation strike in either of these wells can affect multiple devices in that row, increasing the likelihood of a soft error. For example, one NFET device may be used in a latch to hold the true value of a bit and another NFET device in the same book may be used to hold the complementary (inverse) value of the bit, and a single radiation event can upset both NFET devices, causing the latch to change its logical state. The radiation may be, e.g., an alpha particle strike emitted from packaging materials or neutrons originating from cosmic radiation. The soft-error rate (SER) of a data processing system can exceed the combined failure rate of all hard-reliability mechanisms (gate oxide breakdown, electro-migration, etc.). Radiation tolerance has thus become a necessity for meeting robustness targets in advanced systems. All storage elements (random-access memory, latches, etc.) are highly susceptible to soft-error induced failures, but memory arrays are usually protected by error-correction codes (ECCs) while latches are usually not so protected. Soft errors in latches are accordingly the major contributors to overall system SER.
Information stored in latches may include control, status or mode bits. For example, a data processing system might provide different mode configurations for clock control logic, and clock control latches can account for a significant portion of a microprocessor latch count. These clock buffer modes are set at system power-on and often must maintain their logical value for days or months to ensure proper performance of the local logic circuits. However, the values can be upset during operation due to soft errors. An upset may be correctable by scanning in a new value, but systems may only allow input scanning in a limited manner such as at power-on, meaning that the system must be restarted if a clock control latch becomes incorrectly set. These reliability problems are particularly troublesome for harsher operating environments, such as aerospace systems where there is increased radiation (high-altitude or orbital space).
For transistor book constructions such as those shown in FIG. 2, it is impossible to isolate wells in a book for radiation tolerance due to vertical well sharing in automated ASIC methodology. Consequently, the only effective way to achieve superior radiation tolerance is by full custom placement, i.e., breaking up logic books into individual gates, which significantly increases the time and cost for design and production of the circuit. It would, therefore, be desirable to devise an improved ASIC book design which could provide the advantages associated with programmable structures but offer better isolation of localized semiconductor devices that might otherwise be affected by a radiation strike. It would be further advantageous if the book design could be implemented in a variety of relative sizes and work within existing ASIC methodologies.